This disclosure relates generally to virtual memory systems, and more specifically, to identifying one or more stale entries in an address translation cache within such systems.
Processors may operate in physical or virtual mode. In physical mode, any requested memory address may directly correlate with a physical address within actual system memory (i.e., main memory) without address translation. In virtual mode, any requested memory address may be translated from a virtual address (including an effective address) to a physical address. In virtual mode, when an address is requested, the operating system may determine if the virtual address is located within a page table of the main memory. The page table may store various mappings of virtual addresses to physical addresses as page table entries (PTEs). Accordingly, if the virtual address is located within the page table, a physical address may be obtained.
Because page table lookup may be expensive, a translation cache (e.g., Translation Lookaside Buffer (TLB)) may help data access become more efficient. For every data request, a first set of accesses to main memory may have to occur for data fetching and a second set of accesses to main memory may have to occur for address translation within a page table. An address translation cache, such as a TLB, may help reduce data access cost by bringing translation lookup closer to the processor, thereby reducing translation latency. A TLB is a specialized type of cache within the processor that retains recently-accessed page address translations (i.e., virtual to physical address translations). For a given data request, a search for the data may begin in the processor at the TLB. When a corresponding entry is not found within the TLB, the operating system may then search the main memory within the page table for the corresponding entry.